1. Field of the Invention
This invention relates to a resistance ladder formed on a semiconductor integrated circuit.
2. Description of the Related Art
In the case, for example, where an analog/digital (A/D) converter or a digital/analog (D/A) converter is formed on a one-chip semiconductor integrated circuit, a resistance ladder is used in some of the analog/digital converting section or digital/analog converting section of the converter. The layout of the above conventional resistance ladder is such structure as shown in FIG. 1.
Resistance elements 3-18 are connected in series between a ground terminal 1 and a source terminal 2. Connection parts between the ground terminal 1 and resistance element 3, the resistance elements 10 and 9, the resistance elements 10 and 11, and the resistance elements 18 and 17 are respectively connected to an output line 111 via corresponding switching MOS transistors 95, 96, 97 and 98. Connection parts between the resistance elements 3 and 4, 9 and 8, 11 and 12, and 17 and 16 are respectively connected to an output line 112 via corresponding switching MOS transistors 99, 100, 101 and 102. Connection parts between the resistance elements 4 and 5, 8 and 7, 12 and 13, and 16 and 15 are respectively connected to an output line 113 via corresponding switching MOS transistors 103, 104, 105 and 106. Moreover, connection parts between the resistance elements 5 and 6, 7 and 6, 13 and 14, and 14 and 15 are connected to an output line 114 via corresponding switching MOS transistors 107, 108, 109 and 110. These output lines 111-114 are connected to a mutiplexer 115 which selects one of the output lines. The output from the selected line by the multiplexer 115 is outputted to an output terminal 116 in accordance with a value of a multiplex signal 117 inputted to a multiplexer 115.
When the switching MOS transistor 99 is turned ON in the resistance ladder while the switching MOS transistors 95-110 other than the switching MOS transistor 99 are kept OFF, the voltage impressed to the source terminal 2 is converted to a voltage equal to the sum of the voltage drops at the resistance elements 4-18 and inputted to the multiplexer 115. When the multiplexer 115 selects the output line 112 in compliance with the multiplex signal 117, the voltage of the output line 112 is outputted to the output terminal 116.
The resistance ladder of the above-described structure is disclosed in Japanese Patent Application Laid-Open Nos. 63-156410 (1988) and 2-168708 (1990).
In the arrangement of FIG. 1, it is necessary to provide output lines of the number equal to the number of the resistance elements constituting one row of the resistance ladder. Therefore, the pattern area of the resistance adder disadvantageously increases in order to arrange the output lines within the resistance ladder layout pattern. Moreover, the number of resistance elements forming one row of the resistance ladder is generally larger than that of the rows of the resistance ladder, thus necessitating many output lines. Therefore, in the case where one line should be selected from the above many output lines, the pattern area of the multiplexer layout enlarges in proportional to the number of the output lines, which causes a rise in cost.
In addition, when a node voltage is to be selected by a MOS transistor as in the prior art resistance ladders disclosed in Japanese Patent Application Laid-Open Nos. 63-156410 and 2-168708, it accompanies a demerit that the pattern area increases.